Tuesday, October 13, 2009

EPEPS: Electrical Performance of Electronic Packaging and Systems Conference

(Syndicated content from: http://signal-integrity.tm.agilent.com/2009/epeps-electrical-performance-of-electronic-packaging-and-systems-conference/)

At the Agilent EEsof EDA exhibit at the Electrical Performance of Electronic Packaging and Systems Conference 2009 (EPEPS 2009) we'll demonstrate the "what if" design space exploration workflow using our new statistical eye diagram channel simulator.



You'll see a demo of signal integrity features that are new in ADS 2009 Update 1, including equalizers, and our DDR3 Compliance DesignKit.


Exhibit Dates: October 19-20, 2009

Exhibit Times: 9AM-6PM

Location: Embassy Suites - Portland/Tigard

9000 SW Washington Square Road

Tigard Oregon 97223


Hope you can make it!

Saturday, September 5, 2009

We've Moved! Please Update Your Bookmarks

The overhead of syndicating the content here seems to outweigh the benefits, so this is the last post. Please book mark our source blog Signal Integrity instead. Thanks!

Wednesday, September 2, 2009

GPU-Accelerated Time-Domain Circuit Simulation Paper at CICC

(Syndicated content from: http://signal-integrity-tips.com/2009/gpu-accelerated-time-domain-circuit-simulation-paper-at-cicc/)

IEEE CICC logo


Tired of waiting for your SPICE simulations to complete?


My colleague Rick Poore will be presenting IEEE Custom Integrated Circuits Conference (CICC) paper 20-3 about his work on "GPU-Accelerated Time-Domain Circuit Simulation" in San Jose at 11:05AM on Wednesday, September 16th.


Abstract


Time-domain circuit simulation is dominated by transistor model evaluation. A modern graphics processing unit (GPU) is a parallel, high performance computer suitable for non-graphics tasks. Simulation is sped up by 3-6x by moving transistor evaluation to a GPU. Implications for writing transistor models for good GPU performance are discussed.


Related posts


Tuesday, September 1, 2009

Geometric Form Factor for Transmission Lines

(Syndicated content from: http://signal-integrity-tips.com/2009/geometric-form-factor-for-transmission-lines/)

The concept of a geometric form factor is very useful when thinking about transmission lines. It bundles up all the messy 2D geometry of cross-sections and field line patterns into one scalar quantity that is fixed for a particular configuration. Then you can think about the general concepts without getting bogged down in field integrals and field solvers.


To explore this idea, let’s start with a uniform relative dielectric constant εr like you'd have with stripline. (Later we’ll generalize to the case where the field lines “sees” a mixture of materials, for example dielectric and air for a microstrip.)


First define a unitless geometric form factor, F, such that capacitance per unit length, C, is:

C is epsilon 0 epsilon r / F

…where ε0 is the vacuum permittivity, 8.9pF/m (or 0.22pF/inch) and εr is the relative permittivity (relative dielectric constant), ~4.2 to 4.6 in FR4 glass/resin.


In general, we need a 2D electrostatic solver to determine F but let’s first look at a geometry for which there’s an exact, textbook, analytical solution: a rod of radius a, with its center a distance b above a ground plane like this:

rod above plane

The form factor is:

Form factor for rod above plane

Couple of thing to note about F:

Unitless: F is a function of a geometric ratio, b/a.

Logarithm of a smallish ratio: In practical cases, the numerator and divisor are not of wildly different orders of magnitude. You wouldn’t create a transmission line with a = 1 mm and b = 1 km! No, for the realistic range of values of b/a, the natural logarithm of the function here is of order 1. For example if b=2a, then F is 0.21.


Let's plot it and two other configurations (illustrated below) and you'll see that (apart from the "short circuit" corner case at a = b) the blue curve varies slowly with b/a:


Plot of form factor for rod above plane, coax, and stripline

The neat thing about the form factor is that when you have it for capacitance, you get inductance and impedance “for free.” To see the first of these, consider the propagation velocity, v, which is both:

Form factor for rod above plane

With a little algebra you can see that the inductance per unit length, L is given by:

L = Fμ0

…where μ0 is the vacuum permeability, 1.3 μH/m

Thus, you can think of F as “how inductive the geometry is versus the free space value of 1.”
If F < 1 the geometry is “more capacitive” than free space, if F > 1 it’s “more inductive.”
The second benefits is that once you have L and C, you also have impedance. Again a little algebra shows that:

Form factor for rod above plane

…where Z0 is the vacuum impedance, 377 Ω. The form factor and the relative dielectric constant determine how far the line impedance is from the “natural” value of Ω. A “capacitive” form factor < 1 lowers the impedance, as does a higher relative dielectric constant. If εr = 4.2, and you want Z = 50 Ω, then pick your geometry such that F is 0.27.


If you take the ground plane and wrap it around the rod, you get co-ax:

coaxial cylinders

The form factor (magenta line above) is a bit lower (more capacitive) as you'd expect from bring the ground plane closer.


If instead you squash the rod into a ribbon and put a second ground plane on top, you get stripline:

stripline

The result is a bit less capactive, because the squashing increases the separation from ground.


You can generalize this idea to non-uniform dielectrics by using a blended or “effective” relative dielectric constant. In a future posting, I’ll also show how it’s useful for lumped elements like inductors from flat coils, and short and long solenoids.

Wednesday, August 26, 2009

Hands-on Workshops for Statistical Mode of Channel Simulator ... and More!

(Syndicated content from: http://signal-integrity-tips.com/2009/ands-on-workshops-statistical-mode-channel-simulator/)

We're offering five complementary signal integrity hands-on workshops entitled "Design Using Fast Channel Simulation and Statistical Eye Diagrams." Seating is limited for this complimentary event. Early enrollment is advised.


Why this workshop is important


Signal integrity engineers need to determine ultralow BER contours for thousands of points in the design space in order to select the optimum set of characteristics for transmitter, channel, and receiver. Traditional techniques consume a prohibitively long simulation time. For this reason we’ve implemented a new statistical mode in our Channel Simulator that eliminates the need for long, multi-million-bit simulations. Now you can generate eye diagrams with ultralow BER contours in just a few seconds.


This in-depth hands-on workshop will demonstrate the “what if” design space exploration workflow that our new statistical eye diagram channel simulator enables, and will also cover tools and modes that can be used in exceptional cases (e.g. equalizer adaptation, non-linearity, or specific bit patterns) where statistical eye techniques cannot be applied.


You will get first hand experiencing using signal integrity features that are new in ADS 2009 Update 1 and EMPro 2009, including equalizers, DDR compliance toolkit, and via simulation with 3DEM.


Who should attend this workshop


Signal integrity engineers for multigigabit links who are running into effects previously only seen in RF and microwave circuits.


Dates & Locations


September 15, 2009 - Ottawa, ON

September 22, 2009 - Chelmsford, MA

September 24, 2009 - Minneapolis, MN

September 29, 2009 - Santa Clara, CA

October 1, 2009 - Anaheim, CA


Agenda


All times are local

9:30a.m. - Register/Breakfast

10:00a.m. - Hands-on workshop part 1


  • ADS for signal integrity analysis

  • HSPICE netlist including W-element in ADS

  • Modeling and simulation of a PCI Express Gen2 channel using Channel Simulator in:


    • Bit by bit mode

    • Statistical mode


  • Equalizer, LMS, RLS, and ZF, and equalizer tap coefficient calculation


12:00p.m. - Lunch

1:00p.m. - Workshop part 2


  • Channel optimization for eye diagram and BER

  • HDMI transmitter and how it can be modeled in ADS

  • DDR Compliance Toolkit

  • 3DEM simulation of a via model with EMPro


3:00p.m. - End

Tuesday, August 18, 2009

S-parameters

(Syndicated content from: http://signal-integrity-tips.com/2009/s-parameters/)

Although scattering parameters (S-parameters) have been used by RF and microwave engineers for over 40 years, their adoption still isn't universal in the signal integrity field. With this informal poll I'm hoping to understand what the barriers (if any) are.


[poll id="33"]
[poll id="34"]

In case I've peaked your interest, here are an application note and a seminar presentation on network analysis with S-parameters. They aren't specific to signal integrity, but are nevertheless very useful in signal integrity engineering:


Sunday, August 16, 2009

Web 2.0 Democratization of First Journalism, Now Conferences?

(Syndicated content from: http://signal-integrity-tips.com/2009/web-2-0-democratization-first-journalism-now-conferences/)

The web has democratized journalism by lowering the entry barrier to publishing. Now it seems it's democratizing conferences: just ask a company to donate its cafeteria or auditorium space for an evening, post some notices on the internet, ask people to bring themselves, their ideas, some sandwiches and soda, and -- voilĂ  -- instant conference! Start of a trend? Compare the two weeks' lead time and near zero cost of the announcement below and the 9-month lead time and million dollar budget for, say, DesignCon. Anyway, good luck and power to the people!


Here is Vikash Rungta's announcement in full.



Folks,


1st event FPGACamp is coming up on Aug'26 at Silicon Valley, CA. The topic of the event is "High Speed Serial Interfaces - Protocols, IPs & Devices". The event is going to be vendor neutral & technical.


I am here looking for speakers / recommendation for speakers. We would like to have a segment about : what FPGA designers & board designers should know to minimize the SI risk including termination, layout guidelines, power supply & lab bringup (may be list few challenges in bring-up, and tools to debug).


We certainly would like to stay vendor neutral, so we need someone who is not part of one of the vendors.


The admission & booths are completely FREE, so rest of the folks interested in attending/ setting up a booth RSVP at FPGACamp or LinkedIn Events: FPGA Camp High Speed Serial Interfaces



Event Details


The idea behind FPGA Camp is to bring engineers together and discuss FPGA, mainly NextGen FPGA technology, application, methodology, best practices and challenges. Also provide a location to meet other local FPGA designers to share their stories.


We are hoping that this would act as a platform to bring all the FPGA users together more often.



Agenda


5:30 - 6:00: Registration and demo

6:00 - 7:00 : Tech Talk- "High Speed Serial Interface: Protocols, IPs & Devices"

7:00 - 7:30 : Vendor talk- a brief talks from the vendors offering High Speed Serial Interface devices or IPs. (5 to 10 Mns each).

7:30 - 8:00 : Networking and exhibits



High Speed Serial Interface: Protocols, IPs & Devices



Recent expansion in the video usage and growth in the Internet use have created a demand to move more data faster than ever. To meet this demand, system & chip designers are moving towards high speed serial interfaces such as PCIe, XAUI, Interlaken, XFI, 10GbE etc. With FPGA devices currently supporting speeds upto ~12.5Gb per IO pair, which makes FPGAs a unique choice for the next design.


This talk will focus on familiarizing people with various protocols (both currently used & emerging), IPs & Devices which can be used to solve the next system problem.

The talk will be followed by quick presentations from some of the vendors offering these solutions (no marketing talk, only technical).



Thanks,

Vikash


Tuesday, August 11, 2009

ADS 2009 Update 1 - What's New

(Syndicated content from: http://signal-integrity-tips.com/2009/ads-2009-update-1-whats-new/)
Here's a 10-minute video clip about the new statistical mode for Channel Simulator. It does the work of more than 40-hours of transient (SPICE-like) simulation in 40 seconds!.

Click to play What's New in ADS 2009 Update 1 video


PDF of slides with speaker notes


Right click to download MP4 for your iPod or media player

Monday, August 3, 2009

Which of these conferences are you likely to attend?

(Syndicated content from: http://signal-integrity-tips.com/2009/which-of-these-conferences-are-you-likely-to-attend/)

My hope for this straw poll is that we can form a collective opinion about upcoming conferences. Vote for your favorites then see the tally so far in real time. It isn’t scientific, but I think it will give a good feel for the answer. Comments on this (and any other postings) are welcome. To leave a comment, click on the Comments link at the bottom of the posting.


Plan to attend another conference? Please leave a comment below.


[poll id="32"]

Friday, July 31, 2009

Which of these conferences are you likely to attend?

(Syndicated content from: http://signal-integrity-tips.com/2009/which-of-these-conferences-are-you-likely-to-attend/)

My hope for this straw poll is that we can form a collective opinion about upcoming conferences. Vote for your favorites then see the tally so far in real time. It isn’t scientific, but I think it will give a good feel for the answer. Comments on this (and any other postings) are welcome. To leave a comment, click on the Comments link at the bottom of the posting.


Plan to attend another conference? Please leave a comment below.


[poll id="32"]

Which of these conferences are you likely to attend?

(Syndicated content from: http://signal-integrity-tips.com/2009/which-of-these-conferences-are-you-likely-to-attend/)

My hope for this straw poll is that we can form a collective opinion about upcoming conferences. Vote for your favorites then see the tally so far in real time. It isn’t scientific, but I think it will give a good feel for the answer. Comments on this (and any other postings) are welcome. To leave a comment, click on the Comments link at the bottom of the posting.


Plan to attend another conference? Please leave a comment below.


[poll id="32"]

Which of these conferences are you likely to attend?

(Syndicated content from: http://signal-integrity-tips.com/2009/which-of-these-conferences-are-you-likely-to-attend/)

My hope for this straw poll is that we can form a collective opinion about upcoming conferences. Vote for your favorites then see the tally so far in real time. It isn’t scientific, but I think it will give a good feel for the answer. Comments on this (and any other postings) are welcome. To leave a comment, click on the Comments link at the bottom of the posting.


Plan to attend another conference? Please leave a comment below.


[poll id="32"]

Which of these conferences are you likely to attend?

(Syndicated content from: http://signal-integrity-tips.com/2009/which-of-these-conferences-are-you-likely-to-attend/)
My hope for this straw poll is that we can form a collective opinion about upcoming conferences. Vote for your favorites then see the tally so far in real time. It isn’t scientific, but I think it will give a good feel for the answer. Comments on this (and any other postings) are welcome. To leave a comment, click on the Comments link at the bottom of the posting.

[poll id="32"]

Plan to attend another conference? Please leave a comment below.

Monday, July 6, 2009

Webcast: Signal Integrity Design Using Fast Channel Simulation and Eye Diagram Statistics

(Syndicated content from: http://signal-integrity-tips.com/2009/webcast-signal-integrity-design-using-fast-channel-simulation-and-eye-diagram-statistics/)
Please register for our free webcast:



Signal Integrity Design Using Fast Channel Simulation and Eye Diagram Statistics

Date: July 29, 2009

Time: 11:00 AM - 12:00 PM PT / 2:00 PM - 3:00 PM ET

Abstract:

Improvements to traditional SPICE-type simulation have increased signal integrity channel simulation speeds to thousands of bits per minute. An overnight run can create a million-bit eye diagram and the associated metrics and statistical figures of merit. But signal integrity engineers need to repeat this determination for thousand of points in the design space in order to select the optimum combination of, for example, pre-emphasis, channel characteristics, and equalizer. Therefore, optimization using eye diagram goals requires a channel simulation technique that is orders of magnitude faster than even the fastest SPICE.



This webcast will demonstrate the "what if" design space exploration workflow that our new million-bit-per-minute channel simulator and eye diagram tool enables.



Registration info:

SI-list server mangles URLs containing the equals character, so you can either edit this one:

DELETEMEhttp://event.on24.com/r.htm?e=151461&s=1&k=45AAAF345F3B6FC01400112AD06ED046

...or use this SI-list-friendly shortened URL:

http://bit.ly/chansimwebcast



PS If you've enjoyed reading my blog, could you spend a few seconds giving me your vote? You don't have to be attending the Design Automation Conference to vote in Denali's "EDA Blogger of 2009" contest. Just go to:

http://www.denali.com/en/events/dac/2009/blogger.jsp

Online voting will close at 10:00PM July 27, 2009.

Thanks!

-- Colin

http://signal-integrity-tips.com

Please vote for this blog

(Syndicated content from: http://signal-integrity-tips.com/2009/please-vote-for-this-blog/)

If you enjoy this blog, could to spend a few seconds giving me your vote? You don't have to be attending the Design Automation Conference to vote in Denali's "EDA Blogger of 2009" contest. Just go to:


http://www.denali.com/en/events/dac/2009/blogger.jsp



Online voting will close at 10:00PM July 27, 2009.

Friday, June 19, 2009

Top 10 Reasons NOT to Care About Signal Integrity

(Syndicated content from: http://signal-integrity-tips.com/2009/top-10-reasons-not-to-care-about-signal-integrity/)

10. Hey! My chip meets spec. It's the OEM's job to design it in right.



9. The speed of light is 670,616,629.4 miles per hours. That's really really fast.



8. I never had that problem on my last project, and this revision is only 30% faster.



7. The via stubs doesn't connect to anything. What harm can they do?



6. My PCB vendor specs means I won't have a problem: "Loss tangent - pretty close to zero. Roughness - almost no roughness. Metal resistivity - are you kidding? Copper's a real good conductor."



5. Skin effect? Isn't that something to do with Photoshop?



4. S-parameters? No thanks. Don't you have an RLC SPICE model?



3. 10 picoseconds? Listen to me: 10 picoseconds to ten decimal places is 0.0000000000 seconds.



2. If it doesn't work we can always step up to Rogers' material.



And the number 1 reason NOT to care about signal integrity is:



1. We're hoping lower speed products will make a come back!



TGIF. Have a good weekend! :-)

Thursday, May 28, 2009

Signal Integrity Textbooks

(Syndicated content from: http://signal-integrity-tips.com/2009/signal-integrity-textbooks/)

Here are my thumbnail reviews of some signal integrity textbooks. They reflect my personal views, not those of Agilent. You can add your thoughts in the box below.




  • Timing Analysis and Simulation for Signal Integrity Engineers by Greg Edlund
    This book takes a different approach to signal integrity then the "traditional" Bogatin and Johnson & Graham approach (see below) in that the starting point is not the interconnect, but the prima dona of signal integrity, the flip-flop in the receiving chip. "If I don't see a clean zero or one during my set up and hold periods," lectures the flip-flop, one hand on hip, the other wagging a threatening finger, "I'm going to go metastable." And so the game begins. How to deliver on that demand? Greg's twenty years - and counting - experience as a hands-on signal integrity engineer makes his textbook authoritative and his narrative style makes the book accessible.


  • A Signal Integrity Engineer's Companion Real-Time Test and Measurement and Design Simulation (Geoff Lawday, David Ireland, and Greg Edlund)
    Some of the chapters (2, 4, 9) in this books are the same (give or take a revision or two) as ones in the book above, so this book should be considered if the non-overlapping material is of value to you. Not sure why the publisher "double-dips" in this way.

  • Signal Integrity - Simplified (2ed due for release July 27, 2009) by Eric Bogatin
    It was Eric who coined the phrases "There are two kinds of engineers -- those who have signal integrity problems, and those who will." and (with respect to all signal integrity issues) "It depends."
    I haven't seen the second edition yet, but the first edition has the "traditional" signal integrity focus on the properties of the interconnect, the impairments that it inflicts on the poor signal, and how to design around them within the limits imposed by physical laws. Eric also has a new book coming out in September, "Signal Integrity Characterization Techniques", co-authored with my colleague Mike Resso. I'll review it when I can.
  • High Speed Digital Design: A Handbook of Black Magic and High Speed Signal Propagation: Advanced Black Magic by Howard Johnson and Martin Graham
    Published in 1993 and 2003 respectively, one frustration with these two very popular books is that I can never quite decided whether the latter is volume two of the former, or whether it's the second edition. There's certainly a lot of overlap between the two, but the second isn't a true superset of the first. It smacks of another case of Prentice Hall "double-dipping." Both volumes/editions have a "traditional" focus on the PRBS signal in the frequency- and time-domains, and its interaction with the interconnect. Personally, I prefer the flow of Eric's book for "cover-to-cover" reading, but there's a lot of good reference material and anecdotes here that I dip into when needed.


Other texts that are on my ever expanding to do list. I'll try to add reviews here someday? Or p>

Wednesday, May 20, 2009

Signal Integrity Papers from Agilent ADS User Group Meetings in Rome and Bblingen

(Syndicated content from: http://ping.fm/0Mgo7)

The Agilent ADS User Group Meetings in Rome (13 May) and Böblingen (14-15 May) had three signal integrity papers that the authors have kindly given permission to post here.

Tuesday, May 19, 2009

Using Equivalent Circuits for the Analysis of Complex Power and Signal Integrity Problems

(Syndicated content from: http://ping.fm/jBTWo)
Guest post from Francesco de Paulis and Antonio Orlandi, UAq EMC Laboratory, University of L’Aquila, Italy

At our ADS User Group meeting in Rome May 13th, Francesco de Paulis and Antonio Orlandi, UAq EMC Laboratory, University of L’Aquila, Italy presented a paper Using Equivalent Circuits for the Analysis of Complex Power and Signal Integrity Problems
Using Equivalent Circuits for the Analysis of Complex Power and Signal Integrity Problems
.


They kindly gave me permission to post the slides here


They compare fast circuit simulation with ADS to complex and time consuming 3D models and conclude that ADS is not only a tool for designing. Its flexibility allows its use as tool to investigate the fundamental mechanisms of relevant power and signal integrity issues and that it is a critical tool for engineering

Friday, May 15, 2009

The Trouble With IFFT

(Syndicated content from: http://signal-integrity-tips.com/2009/the-trouble-with-ifft/)
Consider the following MATLAB code which models a lossless delay by its amplitude and phase frequency response, then applies a simple inverse discrete Fourier transform, then plots one period of the time domain response:

close all
clear all
npts = 256;
delta_t = 1e-9; % s
t = 0:delta_t:delta_t*(npts-1);
f = linspace(-(npts-1)/(2*npts*delta_t),1/(2*delta_t),npts); % Hz
amplitude = ones(size(f));
delay = 10.5e-9; %s
phase = -2 * pi * f * delay;
fresp = amplitude .* exp(j * phase);
tresp = ifft(ifftshift(fresp));
plot(t,tresp)

The resulting plot shows that this method cannot be used to create an accurate impulse response:


one period of the time domain response


The pulse is spread out so badly that the skirt of the next period leaks into the end of this one.


The fundamental issues is that to get an impulse response, you have to do an inverse Laplace transform, not an inverse Fourier transform. (The output of an inverse Fourier transform isn’t an impulse response at all: it’s one period of the repeated pulse train response.) "But," you say, "I don't have the frequency response in the complex plane, I only have the steady state response on the upper half of the f = j ω line." Kramers-Kronig relation to the rescue! This relation says that if you have a real physical system i.e. a causal system the frequency response it is possible to construct the impulse response (causal of course) from the steady state data alone.


If you don't want to do the math (and I don't blame you for that), don't worry we've done it for you in ADS (US patent pending, application 20080281893).

Thursday, May 14, 2009

Fifteenth Anniversary of the SI-List

(Syndicated content from: http://ping.fm/LnblX)

The si-list went "on the air" fifteen years ago today, on May 15, 1994 -- an eon in Internet-years. It predates that milestone moment of the Internet: the IPO of Netscape on August 9, 1995.


The genesis was a short course on "Electrical Modeling, Simulation and Design of Electronic Packages" that was taught by Raj Mittra, Paul Franzon and Jose Schutt-Aine in San Jose, CA on May 9-12, 1994. During the last day of class we passed around a blank piece of paper collecting e-mail addresses from anyone who wanted to be included in a proposed signal integrity email list. When I returned to my office at Sun Microsystems the following Monday I put together the initial si-list with about 30 subscribers from the previous week's short course.


Now 15 years later we have about 3,500 subscribers. They range from students just getting their feet wet in engineering to world-renowned experts in the field. They hail from both industry and academia in just about every country in the world that is involved in signal integrity related endeavors.


The original idea was to provide a forum for the exchange of technical conversation related to signal integrity and related fields. Over the years we have endeavored to keep the majority of the list traffic on the technical level and to control the use of the forum for advertising and head-hunting. To that end I think we have been remarkably successful. Let me take this opportunity to remind folk that working engineers and hiring managers looking to add to their staff may post job opening and that postings by 'headhunters' and HR departments are generally discouraged. Postings by vendors (hardware and software) should be primarily technical in nature and should not be mere advertisements. Si-list is not a marketing forum. Vendor postings about commercial products should refer those interested in further information to an e-mail, web address, or phone number for more detailed follow-up.


A bit of behind the scenes history:

  • The original si-list incarnation was implemented as a simple Unix .forward file on an ancient Sparc2 workstation in my office. All list administration (additions, deletions etc.) was done manually.

  • As the list grew,  we transitioned to the Majordomo listserver software and ran the list from a slightly less ancient Sparc4 box located in our SI lab.

  • Over the years the subscriber database and the attendant bandwidth on the net increased. In order to head-off a cease and desist order from the keeper of the Sun LAN, si-list was moved to an external Linux server (freelists.org) running the Ecartis maillist manager software in June 2001. The list still resides on that server today. Thanks to the Freelists admins for years of fine service!




If you want to look back at the postings, archives are available at these locations:



Thanks to all contributors over the past fifteen years.


Happy fifteenth anniversary si-list!


Ed: Related post What Social Media Web Sites Do Signal Integrity Engineers Use?

Monday, May 11, 2009

Evolution of voltage and current

(Syndicated content from: <a href="http://ping.fm/xRXly">http://ping.fm/K18Wr</a>)
<em>Guest post from Peppe, a student in Italy</em>

Hi,

Someone can help me?

This the exercise:
<p style="margin-bottom: 0cm;">In the following transmission lines circuit we assume that the generator Vg is a constant voltage equal to 3.3V and that the switch is closed at S = 0. Starting from the parameters shown in figure, graphics:</p>

<p style="margin-bottom: 0cm;">a) the tension on both lines as a function of x, V(x), for t=0.2ns;
b) the current on the two lines as a function of x, I(x), for t=0.4ns;
c) the line voltage as a function of time, V(t), for x=3cm;
d) the line current as a function of time, I(t), for x=-4cm;
<p style="margin-bottom: 0cm;"></p>
<p style="margin-bottom: 0cm;"></p>
<p style="margin-bottom: 0cm;"></p>

<img src="http://ping.fm/63i18" alt="exercise" width="508" height="274" />

Thursday, April 9, 2009

Simulator speeds eye measurements
Nice write up by Rick Nelson, Editor-in-Chief -- EDN, 4/9/2009

Tuesday, April 7, 2009

April 12th?

(Syndicated content from: http://ping.fm/gwqsL)
What has its anniversary on April 12th? Please post a comment if you know.

Thursday, April 2, 2009

Practical Analysis Of Backplane Vias

(Syndicated content from: http://ping.fm/KsOhJ)

RF Global Net are offering a download the white paper that my Agilent colleagues Sanjeev Gupta and Mike Resso co-wrote with Eric Bogatin and Lambert Simonovich.



Here are the details:



Practical Analysis Of Backplane Vias



By Dr. Eric Bogatin of Bogatin Enterprises, Lambert Simonovich of Nortel, and Sanjeev Gupta and Mike Resso, of Agilent Technologies



In this paper, Dr. Bogatin and his co-authors show how accurate, verified models for vias in a multilayer circuit board are necessary to predict link performance in the multi-gigabit-per-second regime. It describes a method for using measurements on a test vehicle to build a high-bandwidth, scalable model of long vias, including the through- and stub-effects. This model can then be used in Agilent's Advanced Design System for simulation. The methodology provides valuable insight into the root causes of performance limits and how to overcome them.

Thursday, March 12, 2009

Datasheets Anyone?

(Syndicated content from: http://ping.fm/qzX3b)

Being in marketing I get terribly excited when we publish a new datasheet or brochure. Not sure if you do, but just in case here's a list of the brand new, hot-off-the-presses, get-them-quick-before-they're-gone datasheets for the elements of the ADS product family that are applicable to signal integrity.


Friday, February 13, 2009

Free Seminars - Connect to the Agilent Experts - PCI Express, USB and DDR Simulations Made Easy

(Syndicated content from http://signal-integrity-tips.com/2009/free-seminars-connect-to-agilent-experts-pci-express-usb-ddr-simulations-made-easy/)

We're offering free seminars entitled "Connect to the Agilent Experts: PCI Express, USB, and DDR Simulations Made Easy!" in 17 North American Cities, Feb 17-19.

Abstract: Are you involved in high speed serial designs such as PCI Express Gen1/Gen2, USB 3.0 and Memory Designs? This presentation will demonstrates how you can quickly and accurately analyze high speed channels and reduce your product design cycle. Complete serial link analysis including how to select best settings for your Transmit or receive equalization and perform automated measurements will be addressed in this presentation.



PCI Express, USB and DDR Simulations Made Easy: Registration page



  • Cities for Tuesday, February 17, 2009:


    • Toronto, ON

    • LA area - Westlake Village, CA

    • Schaumburg, IL

    • Columbia, MD

    • Seattle area - Bellevue, WA

    • Santa Clara, CA

  • Cities for Wednesday, February 18, 2009:



    • Ottawa, ON

    • Portland, OR

    • LA area - Anaheim, CA


  • Cities for Thursday, February 19, 2009:


    • Ft. Lauderdale area - Sunrise, FL

    • Roseville, CA

    • Santa Clara, CA

    • San Diego, CA

    • Andover, MA


Thursday, January 15, 2009

Meet Us IRL (In Real Life) at DesignCon 2009

(Syndicated content from http://signal-integrity-tips.com/2009/meet-us-irl-in-real-life-at-designcon-2009/)

Despite rumors from some Web 2.0 fanatics that it isn't necessary, you can still actually meet people "IRL" (in real life) not just virtually via the web. My Agilent colleagues and I will be staffing Booth #305 at DesignCon 2009, in Santa Clara CA, Feb 2-5 2009. Stop by and say hello!



PS: My entry to the DesignCon® 2009 Video Contest is entitled "Day in the Life of an Agilent EEsof EDA Chiphead®". Is there really an upcoming ISO 1984 standard? Find out in this (hopefully) hilarious parody of a famous series of YouTube videos.













PPS: Here are the Agilent papers and panels. Example: "7-TA2" means track 7, Tuesday AM, paper 2.



  • 7-TA2: "Practical Analysis of Backplane Vias for 5 Gbps and Above", Eric Bogatin, Sanjeev Gupta (EEsof), Mike Resso (CTD)

  • 8-TA1: "The use of Optimization in Signal Integrity performance Centric High Speed Digital Design Flows", Brahim Bensalem (Intel), Sanjeev Gupta (EEsof)

  • 8-TA3: "Analysis of Random Noise and the Effect of Band-Limited Noise on Stressed-Eye Receiver Tolerance Test", Ransom Stephens, Marcus Mueller (DTD_DPT)

  • 13-TA4: "Verify your signal integrity margins: De-embedding of fixtures and probing in a real time digital oscilloscope", Jim Choate (DTD_Scopes)

  • 12-WA2: "VNA Characterization of Cable Assemblies for Supercomputer Applications", Greg Edlund (IBM), Mike Resso (CTD)

  • 12-WA3: "Characterizing Non-Standard Impedance Channels with 50 Ohm Instruments", Julian Ferry (Samtec), Mike Resso (CTD), OJ Danzy (CTD)

  • 7-WA4: "BER Performances for High-Speed Serial Link System Estimated by using Quasi-Analytical Method", Ding-qing Lu (EEsof)

  • 12-THA2: "A Comparison of Fixture Removal Methods for Characterization of Differential PCB Channels", Weiping Hou (Huawei), Quan-Li Li (Agilent China)

  • TF-MA4: "Fixturing and Calibration Techniques for Obtaining Wide Bandwidth Measured Data for Time Domain Simulations and Measurement-Based Modeling", Heidi Barnes (Verigy), Sanjeev Gupta (EEsof), Mike Resso (CTD)

  • TP-MP: "The case of the closing eye - Addressing the Industry's Next Gen Serial Data Design Validation Challenges", Chris Loberg (Tek), Karl Kachigan (DTD)

  • TP-WP: "Do it right or do it over? Signal integrity engineer in the era of highly compressed project schedules", Colin Warwick (EEsof)

Tuesday, January 6, 2009

Open the Eye Solution - Mark Broman

(Syndicated content from http://signal-integrity-tips.com/2009/open-the-eye-solution-mark-broman/)
Mark Broman of Thin Film Technology Corp submitted this solution to our puzzle contest. Mark writes:



This puzzle appears to be a classic lossy ISI problem. We work with these all the time. So much so that we developed a line of high pass filters that are the inverse function of the typical bessel loss of a transmission line. We plot the S-parameters and mark the loss point of the fundamental frequency of the expected data rate. We then use a measured model of this filter part with the channel measurement to show the expected eye using this filter.


ADS schematics and resulting eye diagram


This is very easy and took about 3 minutes, 10 minutes tops if you count installing the model library. This is not the tightest solution but is still very effective and the simulation is done from measured models on both ends. Our experience is that 10db channel loss budget are pretty standard but this one is 15dB. The simulated TDR of the trace shows an impedance discontinuity that is most likely a via stub that pushes the loss down and out of budget.