Tuesday, October 13, 2009

EPEPS: Electrical Performance of Electronic Packaging and Systems Conference

(Syndicated content from: http://signal-integrity.tm.agilent.com/2009/epeps-electrical-performance-of-electronic-packaging-and-systems-conference/)

At the Agilent EEsof EDA exhibit at the Electrical Performance of Electronic Packaging and Systems Conference 2009 (EPEPS 2009) we'll demonstrate the "what if" design space exploration workflow using our new statistical eye diagram channel simulator.



You'll see a demo of signal integrity features that are new in ADS 2009 Update 1, including equalizers, and our DDR3 Compliance DesignKit.


Exhibit Dates: October 19-20, 2009

Exhibit Times: 9AM-6PM

Location: Embassy Suites - Portland/Tigard

9000 SW Washington Square Road

Tigard Oregon 97223


Hope you can make it!

Saturday, September 5, 2009

We've Moved! Please Update Your Bookmarks

The overhead of syndicating the content here seems to outweigh the benefits, so this is the last post. Please book mark our source blog Signal Integrity instead. Thanks!

Wednesday, September 2, 2009

GPU-Accelerated Time-Domain Circuit Simulation Paper at CICC

(Syndicated content from: http://signal-integrity-tips.com/2009/gpu-accelerated-time-domain-circuit-simulation-paper-at-cicc/)

IEEE CICC logo


Tired of waiting for your SPICE simulations to complete?


My colleague Rick Poore will be presenting IEEE Custom Integrated Circuits Conference (CICC) paper 20-3 about his work on "GPU-Accelerated Time-Domain Circuit Simulation" in San Jose at 11:05AM on Wednesday, September 16th.


Abstract


Time-domain circuit simulation is dominated by transistor model evaluation. A modern graphics processing unit (GPU) is a parallel, high performance computer suitable for non-graphics tasks. Simulation is sped up by 3-6x by moving transistor evaluation to a GPU. Implications for writing transistor models for good GPU performance are discussed.


Related posts


Tuesday, September 1, 2009

Geometric Form Factor for Transmission Lines

(Syndicated content from: http://signal-integrity-tips.com/2009/geometric-form-factor-for-transmission-lines/)

The concept of a geometric form factor is very useful when thinking about transmission lines. It bundles up all the messy 2D geometry of cross-sections and field line patterns into one scalar quantity that is fixed for a particular configuration. Then you can think about the general concepts without getting bogged down in field integrals and field solvers.


To explore this idea, let’s start with a uniform relative dielectric constant εr like you'd have with stripline. (Later we’ll generalize to the case where the field lines “sees” a mixture of materials, for example dielectric and air for a microstrip.)


First define a unitless geometric form factor, F, such that capacitance per unit length, C, is:

C is epsilon 0 epsilon r / F

…where ε0 is the vacuum permittivity, 8.9pF/m (or 0.22pF/inch) and εr is the relative permittivity (relative dielectric constant), ~4.2 to 4.6 in FR4 glass/resin.


In general, we need a 2D electrostatic solver to determine F but let’s first look at a geometry for which there’s an exact, textbook, analytical solution: a rod of radius a, with its center a distance b above a ground plane like this:

rod above plane

The form factor is:

Form factor for rod above plane

Couple of thing to note about F:

Unitless: F is a function of a geometric ratio, b/a.

Logarithm of a smallish ratio: In practical cases, the numerator and divisor are not of wildly different orders of magnitude. You wouldn’t create a transmission line with a = 1 mm and b = 1 km! No, for the realistic range of values of b/a, the natural logarithm of the function here is of order 1. For example if b=2a, then F is 0.21.


Let's plot it and two other configurations (illustrated below) and you'll see that (apart from the "short circuit" corner case at a = b) the blue curve varies slowly with b/a:


Plot of form factor for rod above plane, coax, and stripline

The neat thing about the form factor is that when you have it for capacitance, you get inductance and impedance “for free.” To see the first of these, consider the propagation velocity, v, which is both:

Form factor for rod above plane

With a little algebra you can see that the inductance per unit length, L is given by:

L = Fμ0

…where μ0 is the vacuum permeability, 1.3 μH/m

Thus, you can think of F as “how inductive the geometry is versus the free space value of 1.”
If F < 1 the geometry is “more capacitive” than free space, if F > 1 it’s “more inductive.”
The second benefits is that once you have L and C, you also have impedance. Again a little algebra shows that:

Form factor for rod above plane

…where Z0 is the vacuum impedance, 377 Ω. The form factor and the relative dielectric constant determine how far the line impedance is from the “natural” value of Ω. A “capacitive” form factor < 1 lowers the impedance, as does a higher relative dielectric constant. If εr = 4.2, and you want Z = 50 Ω, then pick your geometry such that F is 0.27.


If you take the ground plane and wrap it around the rod, you get co-ax:

coaxial cylinders

The form factor (magenta line above) is a bit lower (more capacitive) as you'd expect from bring the ground plane closer.


If instead you squash the rod into a ribbon and put a second ground plane on top, you get stripline:

stripline

The result is a bit less capactive, because the squashing increases the separation from ground.


You can generalize this idea to non-uniform dielectrics by using a blended or “effective” relative dielectric constant. In a future posting, I’ll also show how it’s useful for lumped elements like inductors from flat coils, and short and long solenoids.

Wednesday, August 26, 2009

Hands-on Workshops for Statistical Mode of Channel Simulator ... and More!

(Syndicated content from: http://signal-integrity-tips.com/2009/ands-on-workshops-statistical-mode-channel-simulator/)

We're offering five complementary signal integrity hands-on workshops entitled "Design Using Fast Channel Simulation and Statistical Eye Diagrams." Seating is limited for this complimentary event. Early enrollment is advised.


Why this workshop is important


Signal integrity engineers need to determine ultralow BER contours for thousands of points in the design space in order to select the optimum set of characteristics for transmitter, channel, and receiver. Traditional techniques consume a prohibitively long simulation time. For this reason we’ve implemented a new statistical mode in our Channel Simulator that eliminates the need for long, multi-million-bit simulations. Now you can generate eye diagrams with ultralow BER contours in just a few seconds.


This in-depth hands-on workshop will demonstrate the “what if” design space exploration workflow that our new statistical eye diagram channel simulator enables, and will also cover tools and modes that can be used in exceptional cases (e.g. equalizer adaptation, non-linearity, or specific bit patterns) where statistical eye techniques cannot be applied.


You will get first hand experiencing using signal integrity features that are new in ADS 2009 Update 1 and EMPro 2009, including equalizers, DDR compliance toolkit, and via simulation with 3DEM.


Who should attend this workshop


Signal integrity engineers for multigigabit links who are running into effects previously only seen in RF and microwave circuits.


Dates & Locations


September 15, 2009 - Ottawa, ON

September 22, 2009 - Chelmsford, MA

September 24, 2009 - Minneapolis, MN

September 29, 2009 - Santa Clara, CA

October 1, 2009 - Anaheim, CA


Agenda


All times are local

9:30a.m. - Register/Breakfast

10:00a.m. - Hands-on workshop part 1


  • ADS for signal integrity analysis

  • HSPICE netlist including W-element in ADS

  • Modeling and simulation of a PCI Express Gen2 channel using Channel Simulator in:


    • Bit by bit mode

    • Statistical mode


  • Equalizer, LMS, RLS, and ZF, and equalizer tap coefficient calculation


12:00p.m. - Lunch

1:00p.m. - Workshop part 2


  • Channel optimization for eye diagram and BER

  • HDMI transmitter and how it can be modeled in ADS

  • DDR Compliance Toolkit

  • 3DEM simulation of a via model with EMPro


3:00p.m. - End

Tuesday, August 18, 2009

S-parameters

(Syndicated content from: http://signal-integrity-tips.com/2009/s-parameters/)

Although scattering parameters (S-parameters) have been used by RF and microwave engineers for over 40 years, their adoption still isn't universal in the signal integrity field. With this informal poll I'm hoping to understand what the barriers (if any) are.


[poll id="33"]
[poll id="34"]

In case I've peaked your interest, here are an application note and a seminar presentation on network analysis with S-parameters. They aren't specific to signal integrity, but are nevertheless very useful in signal integrity engineering: